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? semiconductor components industries, llc, 2013 august, 2013 ? rev . 0 1 publication order number: nb3n1200k/d nb3n1200k, NB3W1200L 3.3 v 100/133 mhz dif fer ential 1:12 hcsl or push-pull clock zdb/fanout buf fer for pcle description the nb3n1200k and NB3W1200L dif ferential clock buf fers are db1200z and db1200zl compliant and are designed to work in conjunction with a pcie compliant source clock synthesizer to provide point ? to ? point clocks to multiple agents. the device is capable of distributing the reference clocks for intel ? quickpath interconnect (intel qpi), pcie gen1/gen2/gen3, sas, sa t a, and intel scalable memory interconnect (intel smi) applications. the vco of the device is optimized to support 100 mhz and 133 mhz frequency operation. the nb3n1200k and NB3W1200L utilize pseudo ? external feedback topology to achieve low input ? to output delay variation. the nb3n1200k is configured with the hcsl buf fer type, while the NB3W1200L is configured with the low ? power nmos push ? pull buf fer type. features ? 12 dif ferential clock output pairs @ 0.7 v ? hcsl compatible outputs for nb3n1200k ? low ? power nmos push ? pull compatible outputs for NB3W1200L ? optimized 100 mhz and 133 mhz operating frequencies to meet the next generation pcie gen 2/gen 3 and intel qpi phase jitter ? db1200z and db1200zl compliant ? 3.3 v 5% supply v oltage operation ? fixed ? feedback for lowest input ? to ? output delay v ariation ? smbus programmable configurations to allow multiple buf fers in a single control network ? pll bypass configurable for pll or fanout operation ? programmable pll bandwidth ? 2 t r i ? level addresses selection (9 smbus addresses) ? individual oe control pin for each of 12 outputs ? low phase jitter (intel qpi, pcie gen 2/gen 3 phase jitter compliant) ? 50 ps max output ? to ? output skew performa nce ? 50 ps max cycle ? to ? cycle jitter (pll mode) ? 100 ps input to output delay v ariation performance ? qfn 64 ? pin package, 9 mm x 9 mm ? spread spectrum compatible: t racks input clock spreading for low emi ? 0 c to +70 c ambient operating t emperature ? these devices are pb ? free and are rohs compliant http://onsemi.com qfn64 mn suffix case 485dh device package shipping ? ordering informa tion nb3n1200kmng qfn ? 64 (pb ? free) 260 units / tray marking diagrams ? for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification brochure, brd801 1/d. nb3n1200kmntxg qfn ? 64 (pb ? free) 1000 / tape & reel NB3W1200Lmng qfn ? 64 (pb ? free) 260 units / tray NB3W1200Lmntxg qfn ? 64 (pb ? free) 1000 / tape & reel 1 64 nb3n 1200k awlyywwg 1 nb3x1200x= specific device code a = assembly location wl = w afer lot yy = y ear ww = w ork w eek g = pb ? free package nb3w 1200l awlyywwg 1 http://
nb3n1200k, NB3W1200L http://onsemi.com 2 figure 1. simplified block diagram iref** fb_out* dif_[11:0] control logic clk_in ssc compatible pll 12 sa_0 sa_1 sda scl mux * fb_out pins are for nb3n1200k only; they are nc for NB3W1200L ** iref pin is for nb3n1200k only; it is nc for NB3W1200L 100m_133m# pwrgd/pwrdn# hbw_byp ass_lbw# oe_[1 1:0]# clk_in# dif_[1 1:0]# r ref fb_out#*
nb3n1200k, NB3W1200L http://onsemi.com 3 nb3n1200k gnd dif_7# dif_7 oe_7# oe_6# dif_6# dif_6 gnd vdd dif_5# dif_5 oe_5# oe_4# dif_4# dif_4 gnd dif_1 1# dif_1 1 oe_1 1# oe_10# dif_10# dif_10 gnd vdd vdd dif_9# dif_9 oe_9# oe_8# dif_8# dif_8 vdd exposed pad (ep) (t op v iew) dif_0 dif_0# oe_0# oe_1# dif_1 dif_1# gnd vdd vdd dif_2 dif_2# oe_2# oe_3# dif_3 dif_3# vdd vdda gnda iref 100m_133m# hbw_byp ass_lbw# pwrgd/pwrdn# gnd vddr clk_in clk_in# sa_0 sda scl sa_1 fb_out# fb_out pin connections NB3W1200L gnd dif_7# dif_7 oe_7# oe_6# dif_6# dif_6 gnd vdd dif_5# dif_5 oe_5# oe_4# dif_4# dif_4 gnd dif_1 1# dif_1 1 oe_1 1# oe_10# dif_10# dif_10 gnd vdd vdd_io dif_9# dif_9 oe_9# oe_8# dif_8# dif_8 vdd_io exposed pad (ep) (t op v iew) dif_0 dif_0# oe_0# oe_1# dif_1 dif_1# gnd vdd vdd_io dif_2 dif_2# oe_2# oe_3# dif_3 dif_3# vdd_io vdda gnda nc 100m_133m# hbw_byp ass_lbw# pwrgd/pwrdn# gnd vddr clk_in clk_in# sa_0 sda scl sa_1 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 62 60 58 56 54 52 50 49 63 61 59 57 55 53 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 62 60 58 56 54 52 50 49 63 61 59 57 55 53 51 figure 2. nb3n1200k pinout: qfn ? 64 (t op v iew) figure 3. NB3W1200L pinout: qfn ? 64 (t op v iew)
nb3n1200k, NB3W1200L http://onsemi.com 4 t able 1. nb3n1200k pin descriptions pin number pin name type description 1 vdda 3.3 v 3.3 v power supply for pll . 2 gnda gnd ground for pll . 3 iref i a precision resistor is attached to this pin to set the dif ferential output current . use r ref = 475 , 1% for 1 0 0 ohms trace. use r ref = 412 , 1% for 85 ohms trace. 4 1 00 m_133m# i , se input/output frequency selection (fs). an external pull ? up or pull ? down resistor is attached to this pin to select the input/output frequency . high = 1 00 mhz output low = 133 mhz output 5 hbw_bypass_lbw# i , se tr i ? level input for selecting the pll bandwidth or bypass mode (refer to tri ? level threshold in t able 4). high = high bw mode med = bypass mode low = low bw mode 6 pwrgd / pwrdn# i , se 3.3 v l vttl input to power up or power down the device. 7 gnd gnd ground for outputs. 8 vddr vdd 3.3 v power supply for receiver . 9 clk_in i , dif 0.7 v differential true input 10 clk_in# i , dif 0.7 v dif ferential complementary input 11 sa_ 0 i , se 3 . 3 v l vttl input selecting the address. tri ? level input (refer to tri ? level threshold in table 4 .) 12 sda i/o open collector smbus data . 13 scl i/o smbus slave clock input . 14 sa_1 i , se 3 . 3 v l vttl input selecting the address. tri ? level input (refer to tri ? level threshold in table 4 .) 15 fb_out# o, dif complementary feedback out pin, termination required. see external feedback termination section . 16 fb_out o, dif t rue feedback out pin, termination required. see external feedback termination section . 17 dif_0 o, dif 0.7 v differential true clock output 18 dif_0# o, dif 0.7 v dif ferential complementary clock output 19 oe_0# i , se 3 . 3 v l vttl active low input for enabling dif output pair 0 . 0 enables outputs, 1 disables outputs. internal pull down. 20 oe_1# i , se 3 . 3 v l vttl active low input for enabling dif output pair 1. 0 enables outputs, 1 disables outputs. internal pull down. 21 dif_1 o, dif 0.7 v differential true clock output 22 dif_1# o, dif 0.7 v dif ferential complementary clock output 23 gnd gnd ground for outputs. 24 vdd 3.3 v 3.3 v power supply for outputs. 25 vdd 3.3 v 3.3 v power supply for outputs. 26 dif_2 o, dif 0.7 v differential true clock output 27 dif_2# o, dif 0.7 v dif ferential complementary clock output 28 oe_2# i , se 3 . 3 v l vttl active low input for enabling dif output pair 2. 0 enables outputs, 1 disables outputs. internal pull down. 29 oe_3# i , se 3 . 3 v l vttl active low input for enabling dif output pair 3. 0 enables outputs, 1 disables outputs. internal pull down. 30 dif_3 o, dif 0.7 v differential true clock output 31 dif_3# o, dif 0.7 v dif ferential complementary clock output 32 vdd 3.3 v 3.3 v power supply for outputs. 33 gnd gnd ground for outputs.
nb3n1200k, NB3W1200L http://onsemi.com 5 t able 1. nb3n1200k pin descriptions pin number description t ype pin name 34 dif_4 o, dif 0.7 v differential true clock output 35 dif_4# o, dif 0.7 v dif ferential complementary clock output 36 oe_4# i, se 3 . 3 v l vttl active low input for enabling dif output pair 4. 0 enables outputs, 1 disables outputs. internal pull down. 37 oe_5# i, se 3 . 3 v l vttl active low input for enabling dif output pair 5. 0 enables outputs, 1 disables outputs. internal pull down. 38 dif_5 o, dif 0.7 v differential true clock output 39 dif_5# o, dif 0.7 v dif ferential complementary clock output 40 vdd 3.3 v 3.3 v power supply for outputs. 41 gnd gnd ground for outputs. 42 dif_6 o, dif 0.7 v differential true clock output 43 dif_6# o, dif 0.7 v dif ferential complementary clock output 44 oe_6# i, se 3 . 3 v l vttl active low input for enabling dif output pair 6. 0 enables outputs, 1 disables outputs. internal pull down. 45 oe_7# i, se 3 . 3 v l vttl active low input for enabling dif output pair 7. 0 enables outputs, 1 disables outputs. internal pull down. 46 dif_7 o, dif 0.7 v differential true clock output 47 dif_7# o, dif 0.7 v dif ferential complementary clock output 48 gnd gnd ground for outputs. 49 vdd 3.3 v 3.3 v power supply for outputs. 50 dif_8 o, dif 0.7 v differential true clock output 51 dif_8# o, dif 0.7 v dif ferential complementary clock output 52 oe_8# i, se 3 . 3 v l vttl active low input for enabling dif output pair 8. 0 enables outputs, 1 disables outputs. internal pull down. 53 oe_9# i, se 3 . 3 v l vttl active low input for enabling dif output pair 9. 0 enables outputs, 1 disables outputs. internal pull down. 54 dif_9 o, dif 0.7 v differential true clock output 55 dif_9# o, dif 0.7 v dif ferential complementary clock output 56 vdd 3.3 v 3.3 v power supply for outputs. 57 vdd 3.3 v 3.3 v power supply for outputs. 58 gnd gnd ground for outputs. 59 dif_10 o, dif 0.7 v differential true clock output 60 dif_10# o, dif 0.7 v dif ferential complementary clock output 61 oe_1 0 # i, se 3 . 3 v l vttl active low input for enabling dif output pair 10. 0 enables outputs, 1 disables outputs. internal pull down. 62 oe_11# i, se 3 . 3 v l vttl active low input for enabling dif output pair 1 1 . 0 enables outputs, 1 disables outputs. internal pull down. 63 dif_11 o, dif 0.7 v differential true clock output 64 dif_11# o, dif 0.7 v dif ferential complementary clock output ep exposed pad thermal the exposed pad (ep) on the qfn ? 64 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to the die, and must be electrically and thermally connected to gnd on the pc board.
nb3n1200k, NB3W1200L http://onsemi.com 6 t able 2. NB3W1200L pin descriptions pin number pin name type description 1 vdda 3.3 v 3.3 v power supply for pll . 2 gnda gnd ground for pll . 3 nc i/o no connect 4 1 00 m_133m# i , se 3 . 3 v tolerant inputs for input/output frequency selection (fs). an external pull ? up or pull ? down resistor is attached to this pin to select the input/output frequency . high = 1 00 mhz output low = 133 mhz output 5 hbw_bypass_lbw# i , se tr i ? level input for selecting the pll bandwidth or bypass mode (refer to tri ? level threshold in t able 4). high = high bw mode, med = bypass mode, low = low bw mode 6 pwrgd / pwrdn# i 3.3 v l vttl input to power up or power down the device. 7 gnd gnd ground for outputs. 8 vddr vdd 3.3 v power supply for receiver . 9 clk_in i , dif 0.7 v differential true input 10 clk_in# i , dif 0.7 v dif ferential complementary input 11 sa_ 0 i 3 . 3 v l vttl input selecting the address. tri ? level input (refer to tri ? level threshold in table 4 .) 12 sda i/o open collector smbus data . 13 scl i/o smbus slave clock input . 14 sa_1 i 3 . 3 v l vttl input selecting the address. t r i ? level input (refer to tri ? level threshold in table 4 .) 15 nc i/o no connect. there are active signals on pin 15; do not connect anything to this pin. 16 nc i/o no connect. there are active signals on pin 16; do not connect anything to this pin. 17 dif_0 o, dif 0.7 v differential true clock output 18 dif_0# o, dif 0.7 v dif ferential complementary clock output 19 oe_0# i , se 3 . 3 v l vttl active low input for enabling dif output pair 0. 0 enables outputs, 1 disables outputs. internal pull down. 20 oe_1# i , se 3 . 3 v l vttl active low input for enabling dif output pair 1. 0 enables outputs, 1 disables outputs. internal pull down. 21 dif_1 o, dif 0.7 v differential true clock output 22 dif_1# o, dif 0.7 v dif ferential complementary clock output 23 gnd gnd ground for outputs. 24 vdd 3.3 v 3.3 v power supply for core. 25 vdd_io vdd power supply for dif ferential outputs. 26 dif_2 o, dif 0.7 v differential true clock output 27 dif_2# o, dif 0.7 v dif ferential complementary clock output 28 oe_2# i , se 3 . 3 v l vttl active low input for enabling dif output pair 2. 0 enables outputs, 1 disables outputs. internal pull down. 29 oe_3# i , se 3 . 3 v l vttl active low input for enabling dif output pair 3. 0 enables outputs, 1 disables outputs. internal pull down. 30 dif_3 o, dif 0.7 v differential true clock output 31 dif_3# o, dif 0.7 v dif ferential complementary clock output 32 vdd_io vdd power supply for dif ferential outputs. 33 gnd gnd ground for outputs.
nb3n1200k, NB3W1200L http://onsemi.com 7 t able 2. NB3W1200L pin descriptions pin number description t ype pin name 34 dif_4 o, dif 0.7 v differential true clock output 35 dif_4# o, dif 0.7 v dif ferential complementary clock output 36 oe_4# i, se 3 . 3 v l vttl active low input for enabling dif output pair 4. 0 enables outputs, 1 disables outputs. internal pull down. 37 oe_5# i, se 3 . 3 v l vttl active low input for enabling dif output pair 5. 0 enables outputs, 1 disables outputs. internal pull down. 38 dif_5 o, dif 0.7 v differential true clock output 39 dif_5# o, dif 0.7 v dif ferential complementary clock output 40 vdd 3.3 v 3.3 v power supply for core. 41 gnd gnd ground for outputs. 42 dif_6 o, dif 0.7 v differential true clock output 43 dif_6# o, dif 0.7 v dif ferential complementary clock output 44 oe_6# i, se 3 . 3 v l vttl active low input for enabling dif output pair 6. 0 enables outputs, 1 disables outputs. internal pull down. 45 oe_7# i, se 3 . 3 v l vttl active low input for enabling dif output pair 7. 0 enables outputs, 1 disables outputs. internal pull down. 46 dif_7 o, dif 0.7 v differential true clock output 47 dif_7# o, dif 0.7 v dif ferential complementary clock output 48 gnd gnd ground for outputs. 49 vdd_io vdd power supply for dif ferential outputs. 50 dif_8 o, dif 0.7 v differential true clock output 51 dif_8# o, dif 0.7 v dif ferential complementary clock output 52 oe_8# i, se 3 . 3 v l vttl active low input for enabling dif output pair 8. 0 enables outputs, 1 disables outputs. internal pull down. 53 oe_9# i, se 3 . 3 v l vttl active low input for enabling dif output pair 9. 0 enables outputs, 1 disables outputs. internal pull down. 54 dif_9 o, dif 0.7 v differential true clock output 55 dif_9# o, dif 0.7 v dif ferential complementary clock output 56 vdd_io vdd power supply for dif ferential outputs. 57 vdd 3.3 v 3.3 v power supply for core. 58 gnd gnd ground for outputs. 59 dif_10 o, dif 0.7 v differential true clock output 60 dif_10# o, dif 0.7 v dif ferential complementary clock output 61 oe_10# i, se 3 . 3 v l vttl active low input for enabling dif output pair 10. 0 enables outputs, 1 disables outputs. internal pull down. 62 oe_11# i, se 3 . 3 v l vttl active low input for enabling dif output pair 1 1 . 0 enables outputs, 1 disables outputs. internal pull down. 63 dif_11 o, dif 0.7 v differential true clock output 64 dif_11# o, dif 0.7 v dif ferential complementary clock output ep exposed pad thermal the exposed pad (ep) on the qfn ? 64 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to the die, and must be electrically and thermally connected to gnd on the pc board.
nb3n1200k, NB3W1200L http://onsemi.com 8 t able 3. maximum ra tings symbol parameter condition min max units v dd /v dda /v ddr core supply voltage 4.6 v v dd_io i/o supply voltage 4.6 v v ih (note 1) input high voltage 4.6 v v ihsmb smb input high voltage sda, scl pins 5.5 v v il 3 . 3 v input low voltage ? 0.5 v ts storage temperature ? 65 150 c esd prot . input esd protection human body model 2000 v i outmax maximum output current nb3n1200k NB3W1200L powerdown mode (pwrgd/pwrdn# = 0) all pairs t r i ? stated all pairs tri ? state low/low 24 12 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only . functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability . 1. maximum vih is not to exceed maximum vdd. t able 4. dc opera ting characteristics (v dd = v dda = v ddr = 3.3 v 5%, t a = 0 c ? 70 c) symbol parameter condition min max units v dd /v dda /v ddr 3 . 3 v core supply voltage 3.3 v 5% 3.135 3.465 v v dd_io (note 2) i/o supply voltage 1.05 v to 3.3 v 5% 0.975 3.465 v i dd power supply current nb3n1200k NB3W1200L at 133 mhz, c l = 2 pf 330 180 ma i ddpd power down current nb3n1200k NB3W1200L 6 6 ma v ih (note 3) input high voltage, single ? ended inputs 2.0 5.5 v v il (note 3) input low voltage, single ? ended inputs gnd ? 0.3 0.8 v v ihclk_in clk_in/clk_in# high 600 1150 mv v ilclk_in clk_in/clk_in# low ? 300 300 mv i il (note 4) input leakage current 0 < v in < v dd ? 5 +5 a vih_fs (note 5) input high voltage 0 .7 v dd +0.3 v vil_fs (note 5) input low voltage gnd ? 0.3 0.35 v v il_tri (note 6) tri ? level input low voltage 0 0.8 v v im_tri (note 6) tri ? level input med voltage 1 . 2 1.8 v v ih_tri (note 6) tri ? level input high voltage 2 . 2 v dd v v oh (note 7) output high voltage scl, sda i oh = ? 1 ma 2 . 4 v v ol (note 7) output low voltage scl, sda i ol = 1 ma 0.4 v c in (note 8) input capacitance 2.5 4.5 pf c out (note 8) output capacitance 2.5 4.5 pf l pin pin inductance 7 nh ta ambient temperature no airflow 0 70 c 2. v dd_io applies to the low power nmos push ? pull NB3W1200L only . 3. sda, scl, oen#, pwrgd/pwrdn#. 4. input leakage current does not include inputs with pull ? up or pull ? down resistors. 5. 100m_133m# frequency select (fs). 6. sa_0, sa_1, hbw_byp ass_lbw#. 7. signal edge is required to be monotonic when transitioning through this region. 8. ccomp capacitance based on pad metallization and silicon device capacitance. not including package pin capacitance.
nb3n1200k, NB3W1200L http://onsemi.com 9 nb3n1200k / NB3W1200L output relational t iming parameters t able 5. electrical characteristics ? skew and differential jitter parameters (v dd = v dda = v ddr = 3.3 v 5%, t a = 0 ? 70 c) group description min typ max units clk_in, dif[x:0] (notes 9, 10, 12, 13) input ? to ? output delay in pll mode, nominal value ? 100 100 ps clk_in, dif[x:0] (notes 10, 11, 13) input ? to ? output delay in bypass mode, nominal value 2.5 4.5 ns clk_in, dif[x:0] (notes 10, 11, 13) input ? to ? output delay variation in pll mode (over voltage and temperature), nominal value |100| ps clk_in, dif[x:0] (notes 10, 11, 13) input ? to ? output delay variation in bypass mode (over voltage and temperature), nominal value |250| ps dif[1 1:0] (notes 9, 10, 11, 13) output ? to ? output skew across all 12 outputs (common to bypass and pll mode) 0 50 ps 9. measured into fixed 2 pf load capacitance . input to output skew is measured at the first output edge following the corresponding input. 10. measured from dif ferential cross ? point to dif ferential cross ? point. 1 1 . all bypass mode input ? to ? output specs refer to the timing between an input edge and the specific output edge created by it. 12. this parameter is deterministic for a given device. 13. measured with scope averaging on to find mean value.
nb3n1200k, NB3W1200L http://onsemi.com 10 t able 6. low band phase jitter ? pll mode group parameter min typ max units dif (notes 14, 16, 17) output pcie gen1 13 86 ps (p ? p) dif (notes 14, 15, 17, 19) output pcie gen2 low band, 10 khz < f < 1.5 mhz 0.1 3.0 ps rms dif (notes 14, 15, 17, 19) output pcie gen2 high band, 1.5 mhz < f < 50 mhz 0.8 3.1 ps rms high band , 1 . 5 mhz < f < nyquist dif (notes 14, 15, 17, 19) output phase jitter impact ? pcie* gen3 (including pll bw 2 ? 4 mhz, cdr = 10 mhz) 0.18 1.0 ps rms dif (notes 14, 18, 20) output intel qpi & intel smi refclk accumulated jitter (4.8 gb/s or 6.4 gb/s, 100 mhz or 133 mhz, 12 ui) 0.14 0.5 ps rms dif (notes 14, 18) output intel qpi & intel smi refclk accumulated jitter (8 gb/s, 100 mhz, 12 ui) 0.07 0.3 ps rms dif (notes 14, 18) output intel qpi & intel smi refclk accumulated jitter (9.6 gb/s, 100 mhz, 12 ui) 0.06 0.2 ps rms t able 7. additive phase jitter ? byp ass mode group parameter min typ max units dif (notes 14, 16, 17) output pcie gen1 0.04 10 ps (p ? p) dif (notes 14, 15, 17, 19) output pcie gen2 low band, 10 khz < f < 1.5 mhz 0.001 0.3 ps rms dif (notes 14, 15, 17, 19) output pcie gen2 high band, 1.5 mhz < f < 50 mhz 0.002 0.7 ps rms dif (notes 14, 15, 17, 19) output phase jitter impact ? pcie* gen3 0.001 0.3 ps rms dif (notes 14, 18, 20) output intel qpi & intel smi refclk accumulated jitter (4.8 gb/s or 6.4 gb/s, 100 mhz or 133 mhz, 12 ui) 0.001 0.3 ps rms dif (notes 14, 18) output intel qpi & intel smi refclk accumulated jitter (8 gb/s, 100 mhz, 12 ui) 0.001 0.1 ps rms dif (notes 14, 18) output intel qpi & intel smi refclk accumulated jitter (9.6 gb/s, 100 mhz, 12 ui) 0.001 0.1 ps rms 14. post processed evaluation through intel supplied matlab scripts. t ested with nb3n1200k/NB3W1200L driven by a ck420bq or equivalent. 15. pcie gen3 filter characteristics are subject to final ratification by pcisig. please check the pci sig for the latest specif ication. 16. these jitter numbers are defined for a ber of 1e ? 12. measured numbers at a smaller sample size have to be extra polated to this ber target. 17. ? = 0.54 is implying a jitter peaking of 3 db. 18. measuring on 100 mhz output using intel supplied clock template jitter tool. 19. measuring on 100 mhz pcie src output using intel supplied clock jitter tool. 20. measuring on 100 mhz, 133 mhz output using intel supplied clock jitter tool. t able 8. pll bandwidth and peaking group parameter min typ max units dif (note 21) pll jitter peaking (hbw_bypass_lbw# = 0) ? 0.7 2 . 0 db dif (note 21) pll jitter peaking (hbw_bypass_lbw# = 1) ? 0.4 2 . 5 db dif (note 22) pll bandwidth (hbw_bypass_lbw# = 1) 2.0 2.7 4.0 mhz dif (note 22) pll bandwidth (hbw_bypass_lbw# = 0) 0.7 0.9 1 . 4 mhz 21. measured as maximum pass band gain . at frequencies within the loop bw , highest point of magnification is called pll jitter peaking . 22. measured at 3 db down or half power point.
nb3n1200k, NB3W1200L http://onsemi.com 11 t able 9. dif 0.7 v ac timing characteristics (non ? spread or ? 0.5% spread spectrum mode) (v dd = v dda = v ddr = 3.3 v 5%) symbol parameter clk = 100 mhz, 133.33 mhz unit min max tstab (note 44) clock stabilization time 1.8 ms laccuracy (notes 26, 30, 38, 45) long accuracy 100 ppm tabs (notes 26, 27, 30) absolute min/max host clk period no spread 9.94900 for 100 mhz 10.05100 for 100 mhz ns 7.44925 for 133 mhz 7.55075 for 133 mhz ? 0.5% spread 9.49900 for 100 mhz 10.10126 for 100 mhz 7.44925 for 133 mhz 7.58845 for 133 mhz slew_rate (notes 24, 26, 30) diff out slew_rate (see figure 4) 1.0 4.0 v/ns trise / tfall (notes 26, 29, 40) rise and fall time variation 125 ps rise/fall matching (notes 26, 30, 41, 43) 20 % vhigh (notes 26, 29, 32) voltage high (typ 0 .70 volts) 660 850 mv vlow (notes 26, 29, 33) voltage low (typ 0. 0 volts) ? 150 150 mv vmax (note 29) maximum voltage 1150 mv vcross absolute (notes 23, 25, 26, 29, 36) absolute crossing point voltages 250 550 mv vcross relative (notes 26, 28, 29, 36) relative crossing point voltages calc calc total vcross (notes 26, 29, 37) total variation of vcross over all edges 140 mv tccjitter (notes 26, 30, 42) cycle ? to ? cycle jitter 50 ps duty cycle (notes 26, 30) pll and bypass modes 45 55 % toe# latency oe# latency ? diff start after oe# assertion ? diff stop after oe# deassertion 4 12 clocks vovs (notes 26, 29, 34) maximum voltage (overshoot) vhigh + 0.3 v vuds (notes 26, 29, 35) maximum voltage (undershoot) vlow ? 0.3 v vrb (notes 26, 29) ringback voltage 0.2 n/a v 23. measured at crossing point where the instantaneous voltage value of the rising edge of clk equals the falling edge of clk#. 24. measurment taken from dif ferential waveform on a component test board. the slew rate is measured from ? 150 mv to +150 mv on the dif ferential waveform. scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge only valid for rising clk_in and falling clk_in#. signal must be monotonic through the v ol to v oh region for t rise and tfall. 25. this measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is cr ossing. 26. t est configuration is rs = 33 . 2 , rp = 49 . 9 , 2 pf for 100 transmission line; rs = 27 , rp = 42 . 2 , 2 pf for 85 transmission line. 27. the average period over any 1 s period of time must be greater than the minimum and less than the maximum specified period. 28. vcross(rel) min and max are derived using the following, vcross(rel) min = 0.250 + 0.5 (vhavg ? 0.700), vcross(rel) max = 0.550 ? 0.5 (0.700 ? vhavg), (see figure 7). 29. measurement taken from single ended waveform. 30. measurement taken from dif ferential waveform. bypass mode, input duty cycle = 50%. 31. unless otherwise noted, all specifications in this table apply to all processor frequencies. 32. vhigh is defined as the statistical average high value as obtained by using the oscilloscope vhigh math function. 33. vlow is defined as the statistical average low value as obtained by using the oscilloscope vlow math function. 34. overshoot is defined as the absolute value of the maximum voltage. 35. undershoot is defined as the absolute value of the minimum voltage. 36. the crossing point must meet the absolute and relative crossing point specifications simultaneously . 37. vcross is defined as the total variation of all crossing voltages of rising diff and falling diff#. this is the maximum allowed variance in vcross for any particular system. 3 8 . us ing f r equenc y c ounter w i th t h e m eas urement i n terv al e qual o r g r eater t han 0 . 15 s , t a rget f r equenc ies a r e 1 00,000,000 h z , 1 33,333,333 hz . 39. using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 hz, 133,000,000 hz. 40. measured with oscilloscope, averaging of f, using min max statistics. v ariation is the delta between min and max . 41. measured with oscilloscope, averaging on, the dif ference between the rising edge rate (average) of diff versus the falling e dge rate (average) of diff#. measured in a 75 mv window around the crosspoint of diff and diff#. 42. measured with device in pll mode, in byp ass mode jitter is additive. 43. rise/fall matching is derived using the following, 2*(t rise ? tfall) / (t rise + tfall). 44. this i s the time from the valid clk_in input clocks and the assertion of the pwrgd signal level at 1.8 v ? 2.0 v to the time that stabl e clocks are output from the buf fer chip (pll locked). 4 5 . a l l long t erm accuracy specifications are guaranteed with the assumption that the input clock complies with ck410b+/ck420bq accuracy requirements. the nb3n1200k and NB3W1200L itself do not contribute to ppm error.
nb3n1200k, NB3W1200L http://onsemi.com 12 t able 10. clock period ssc disabled ssc off center freq. mhz measurement window units 1 clock 1 s 0.1 s 0.1 s 0.1 s 1 s 1 clock ? jitter c ? c abs per min ? ssc short avg min ? ppm long avg min 0 ppm period + ppm long avg max + ssc short avg max + jitter c ? c abs per max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns t able 1 1. clock period ssc enabled ssc on center freq. mhz measurement window units 1 clock 1 s 0.1 s 0.1 s 0.1 s 1 s 1 clock ? jitter c ? c abs per min ? ssc short avg min ? ppm long avg min 0 ppm period + ppm long avg max + ssc short avg max + jitter c ? c abs per max 99 . 75 9.94900 9.99900 10.02406 10.02506 10.02607 10.05126 10.10126 ns 133.00 7.44925 7.49925 7.51805 7.51880 7.51955 7.53845 7.58845 ns t able 12. input edge ra te (note 46 ) frequency select (fs) min max unit 100 mhz 0.35 n/a v/ns 133 mhz 0.35 n/a v/ns 46. input edge rate is based on single ended measurement . this is the minimum input edge rate at which the nb3n1200k / NB3W1200L devices are guaranteed to meet all performance specifications .
nb3n1200k, NB3W1200L http://onsemi.com 13 measurement points for differential figure 4. single ? ended measurement points for t rise, tfall figure 5. single ? ended measurement points for v ovs , v uds , vr b figure 6. differential (diff x ? diff x #) measurement points (tperiod, duty cycle, jitter) vcross v ovs vhigh vrb vr b vlow vuds tperiod skew measurement point 0.0 v high duty cycle% low duty cycle% voh = 0.525 v vol = 0.175 v diff x diff x # tfall (diff x #) t rise (diff x )
nb3n1200k, NB3W1200L http://onsemi.com 14 figure 7. vcross range clarification vhigh a verage (mv) 825 800 750 725 700 675 650 625 200 250 300 350 450 500 550 crossing point (mv) 775 850 400 600 equ 1: vcross(rel) max = 0.550 ? 0.5(0.7 ? vhavg) equ 2: vcross(rel) min = 0.250 + 0.5(vhavg ? 0.7) vcross(rel) max vcross(rel) min for vhigh < 700 mv use equ. 1 for vhigh > 700 mv use equ. 2 t h e picture above illustrates the ef fect of vhigh above and below 700 mv on the vcross range. the purpose of this is to prevent a 250 mv vcross with an 850 mv vhigh. in addition, this prevents the case of a 550 mv vcross with a 660 mv vhigh. the actual specification for vcross is dependent upon the measured amplitude of vhigh. clk_in, clk_in# t h e d i f ferential input clock is expected to b e s o urced from a clock synthesizer . oe# and output enables (control registers) each output can be individually enabled or disabled by smbus control register bits. additionally , each output of the dif[1 1:0] has a dedicated oe# pin. the oe# pins are asy nchro nous asserted ? low signals. the output enable bits in the smbus registers are active high and are set to enable by default. the disabled state for the nb3n1200k hcsl outputs is hi ? z, with the termination network pulling the outputs low/low . t he disabled state for the NB3W1200L low power nmos push ? pull outputs is low/low . in the following text, if the nb3n1200k hcsl output is referred to as h i ? z or t ri ? state, t he equivalent state of the NB3W1200L nmos push ? pull output is low/low . please note that the logic level for assertion or deassertion is dif ferent in software than it is on hardware. this follows hardware default nomenclature for communication chann els (e.g., output is enabled if oe# pin is pulled low) and still maintains software programming logic (e.g., output is enabled if oe register is tr ue). please refer to t able 1 3 for the truth table for enabling and disabling outputs via hardware and software. note that both the control register bit must be a ?1? and t he oe# pin must be a ?0? for the output to be active. note: the assertion and de ? assertion of this signal is absolutely asynchro nous. t able 13. nb3n1200k oe and power management inputs oe# hardware pins & control register bits outputs pll state pwrgd/ pwrdn# clk_in/ clk_in# smbus enable bit oe# pin dif/dif# [1 1: 0 ] fb_out/ fb_out# 0 x x x hi ? z hi ? z off 1 running 0 x hi ? z running on 1 0 running running on 1 1 hi ? z running on table 14. NB3W1200L power management inputs oe# hardware pins & control register bits outputs pll state pwrgd/ pwrdn# clk_in/ clk_in# smbus enable bit oe# pin dif/dif# [1 1: 0 ] nc pins (pins 15, 16) 0 x x x low/low low/low off 1 running 0 x low/low running on 1 0 running running on 1 1 low/low running on
nb3n1200k, NB3W1200L http://onsemi.com 15 oe# assertion (t ransition from ?1? to ? 0 ?) all dif ferential outputs that were tri ? stated are to resume normal operation in a glitch free manner . the latency from the assertion to active outputs is 4 ? 12 dif clock periods. oe# de - assertion (t ransition from ? 0 ? to ?1?) the impact of de ? asserting oe# is each corresponding output will transition from normal operation to tri ? state in a glitch free manner . a minimum of 4 valid clocks will be provided after the de ? assertion of oe#. the maximum latency from the de ? assertion to tri ? stated outputs is 12 dif clock periods. 100m_133m# ? frequency selection (fs) the nb3n1200k / NB3W1200L is optimized for lowest phase jitter performance at 100 mhz and 133 mhz operating frequencies. t he 100m_133m# is a hardware pin, which programs the appropriate output frequency of the d i f pairs. note that the clk_in freque ncy is equal to clk_out frequency; this mea ns that the nb3n1200k / NB3W1200L is operated in the 1:1 mode only . the frequency selection can be enabled by the 100m_133m# hardware pin. an external pull ? up or pull ? down resistor is attached to this pin to select the input/output frequency . t h e functionality is summarized in t able 1 5 . t able 15. frequency select (fs) program 100m_133m# optimiz ed frequency (clk_in = clk_out) 0 133.33 mhz 1 100.00 mhz note: all dif ferential outputs transition from 100 mhz to 133 mhz or from 133 mhz to 100 mhz in a glitch free manner . sa_0 , sa_1 ? address selection sa_0 and sa_1 are tri ? level hardware pins , which program t he appropriate address for the nb3n1200k / NB3W1200L . t he two tri - level input pins that can configure the nb3n1200k / NB3W1200L to nine dif ferent addresses (refer to t able 4 for v il _t ri , v im _t ri , v ih _t ri signal level) . t able 16. smbus address t able sa_1 sa_0 smbus address l l d8 l m da l h de m l c2 m m c4 m h c6 h l ca h m cc h h ce pwrgd/pwrdn# pwrgd is asserted high and de ? asserted low . de ? assertion of pwrgd (pulling the signal low) is equivalent to indicating a powerdown condition. pwrgd (assertion) is used by the nb3n1200k / NB3W1200L to sample in itial configurations such as freq uency select condition and sa selections. after pwrgd has been asserted high for the first time , t h e pin becomes a pwrdn# (power down) pin that can be used to shut of f all clocks cleanly and instruct the device to invoke power savings mode . pwrdn# is a completely async hronous active low input . when entering power savings mode , pwrdn# should be asserted low prior to shutting off the input clock or power to ens ure all clocks shut down in a glitch free manner . when pwrdn# is asserted l o w , all clocks will be tri - stated prior to turning of f the vco . when pwrdn# is de - asserted high , all clocks will start and stop without any abnormal behavior and will meet all ac and dc parameters . note: the assertion and de - assertion of pwrdn# is absolutely asynchro nous. w arning: disabling of the clk_in input clock prior to assertion of pwrdn# is an undefined mode and not recommended . operation in this mode may result in glitches, excessive freque ncy shifting , etc . t able 17. pwrgd/pwrdn# functionality pwrgd/pwrdn# dif dif# 0 tr i ? state tri ? state 1 normal normal
nb3n1200k, NB3W1200L http://onsemi.com 16 pwrdn# assertion when pwrdn# is sampled low by two consecutive rising edges of dif#, all dif ferential outputs must held tri - stated on the next dif# high to low transition . figure 8. pwrdn#?assertion dif dif# pwrdn# pwrgd assertion the power ? up latency is to be less than 1.8 ms. this is the time from the valid clk_in input clocks and the assertion of the pwrgd signal to the time that stable clocks are output from the buf fer chip (pll locked). all dif ferential outputs stopped in a tri ? state condition resulting from power down must be driven high in less than 300 s of pwrdn# de ? assertion to a voltage greater than 200 mv . figure 9. pwrgd assertion (pwrdown ? de ? assertion) pwrgd dif tdrive_pwrdn# <300 s; >200 mv tstable <1.8 ms dif# hbw_byp ass_lbw# the hbw_byp ass_lbw# is a tri level function input pin (refer to t able 13 for vil_t ri, vim_t ri, vih_t ri ? signal level). it is used to select between pll high bandwidth, bypass mode and pll low bandwidth mode. in the bypass mode, the input clock is passed directly to the output stage which may result in up to 50 ps of additive cycle ? to ? cycle jitter (50 ps + input jitter) on dif outputs. in the case of pll mode, the input clock is passed through a pll to reduce high frequency jitter . the pll hbw , byp ass, and pll lbw mode may be selected by asserting the hbw_byp ass_lbw# input pin to the appropriate level per the following table: t able 18. pll bandwidth and readback t able hbw_byp ass_lbw# pin mode byte 0, bit 7 byte 0, bit 6 l lbw 0 0 m byp ass 0 1 h hbw 1 1 additionally , the nb3n1200k/NB3W1200L has the ability to override the latch value of the pll operating mode from hardware strap pin 5 via use of byte 0, bits 2 and 1 . byte 0 bit 3 must be set to 1 to allow user to change bits 2 and 1 to affect the pll. bits 7 and 6 will always read back the original latched value. a warm reset of the system will have to be accomplished if the user changes these bits.
nb3n1200k, NB3W1200L http://onsemi.com 17 external feedback t ermination nb3n1200k external feedback t ermination the nb3n1200k utilizes fixed external feedback topology to achieve low input ? to ? output delay variation. a normal hcsl termination will be needed on the fb_out/fb_out# pin 15 and pin 16. a combined shunt and series resistors value can be used to form a single termination resistor for the rfb_term. the termination resistor value is the sum of the rs and rp values. for 100 trace impedance line: rs = 33 ; rp = 49.9 therefore, r fb_ t e r m = 82.9 note: use the standard 82.5 , 1% resistor value. for 85 trace impedance line: rs = 27 ; rp = 43.2 therefore, r fb_ t e r m = 70.2 note: use the standard 69.8 , 1% resistor value. figure 10. external feedback example schematic nb3n1200k fb_out r fb_term r fb_term fb_out# t able 19. feedback termina tion resist ors board t race impedance r fb_term units 100 82 . 5 1% 85 69 . 8 1% NB3W1200L feedback t ermination there is no termination resistor needed at pin 15 and pin 1 6 of the NB3W1200L nmos push ? pull low power buf f e r . pin 15 and pin 16 of the NB3W1200L are no connect (nc) pins . these pins have an active signal on them , so they must be left unconnected .
nb3n1200k, NB3W1200L http://onsemi.com 18 byte read/w rite reading or writing a register in a smbus slave device in byte mode always involves specifying the register number . read. t he standard byte read is as s hown in the following figure. it is an exte nsion of t he byte write. the write start co ndition is repeated then the slave device starts sending data and the master acknowledges it until the last byte is sent. the master terminates the transfer with a nak, then a stop condition. for byte operation, the 2*7 th bit of the command byte must be set. for block operations, the 2*7 th bit must be reset. if the bit is not set, the next byte must be the byte transfer count. figure 1 1. byte read protocol t slave wr a command a r slave rd a data byte 0 byte read protocol n p 17 1 1 8 1 1 7 8 11 1 1 start condition command stop condition acknowledge not ack repeat start register # to read 2*7 bit = 1 w rite. the following figure illustrates a simple typical byte write. for byte operation the 2*7th bit of the command byte must b e set . for block operations, the 2*7th bit must be reset. if the bit is not set, the next byte must be the byte transfer count. the count can be between 1 and 32. it is not allowed to be zero or exceed 32. figure 12. byte w rite protocol t slave wr a command a data byte 0 byte write protocol a p 17 118 1 8 1 1 start condition command stop condition acknowledge register # to write 2*7 bit = 1 m to s to master to slave to block read/write read. after the slave address is sent with the r/w condition bit set , the command byte is sent with the msb = 0. the slave ack? s the register index in the command byte. the master sends a repeat start function. after the slave ack? s this, the slave sends t he number of bytes it wants to transfer (>0 and <33). the master ack? s each byte except the last and sends a stop function. figure 13. block read protocol t slave w r a command code a block read protocol 17 1 1 8 1 start condition command acknowledge register # to write 2*7 bit = 0 data byte a a data byte 1 n p 81 8 1 8 1 1 stop condition data byte 0 not acknowledge r slave rd a 17 1 1 repeat start condition
nb3n1200k, NB3W1200L http://onsemi.com 19 w rite. after t he slave address is sent with the r/w condition bit not set, the command byte is sent with the msb = 0. t he lower seven bits indicate what register to start t he transfer at. if the command byte is 00h, the slave device will be compatible with existing block mode slave devices. the next byte of a write must be the count of bytes that the master will transfer to the slave device. the byte count must be greater than zero and less than 33. following this byte are the data bytes to be transferred to t he slave device. the slave device always acknowledges each byte received. t he tra nsfer is terminated after the slave sends t he ack and the master se nds a stop function. figure 14. block w rite protocol t slave address w r a command a block w rite protocol 17 118 1 start condition command bit acknowledge register # to write 2*7 bit = 0 m to s to master to slave to byte count = 2 a a data byte 1 a p 81 8 1 8 1 1 stop condition data byte 0 nb3n1200k/NB3W1200L control register t able 20. byte 0 : frequency select, output enable, pll mode control register bit description if bit = 0 if bit = 1 t ype default output(s) affected 0 100m_133m# frequency select (fs) 133 mhz 100 mhz r latched at power up dif[1 1:0] 1 pll mode 0 see pll operating mode readback t able rw 1 2 pll mode 1 rw 1 3 pll software enable hw latch smbus control rw 0 4 reserved 0 5 reserved 0 6 pll mode 0 see pll operating mode readback t able r latched at power up 7 pll mode 1 see pll operating mode readback t able r latched at power up note: byte 0, bit_[3:1] are bw pll sw enable for the NB3W1200L and nb3n1200k . setting bit 3 to ?1? allows the user to override the latch value from pin 5 via use of bits 2 and 1 . use the values from the pll operating mode readback t able . note that bits 7 and 6 will keep the value originally latched on pin 5. a warm reset of the system will have to be accomplished if the user changes these bits .
nb3n1200k, NB3W1200L http://onsemi.com 20 t able 21. byte 1: output enable control register bit description if bit = 0 if bit = 1 type default output(s) affected 0 output enable dif 0 hi ? z for nb3n1200k enabled rw 1 dif_0, dif_0# low/low for NB3W1200L 1 output enable dif 1 hi ? z for nb3n1200k enabled rw 1 dif_1, dif_1# low/low for NB3W1200L 2 output enable dif 2 hi ? z for nb3n1200k enabled rw 1 dif_2, dif_2# low/low for NB3W1200L 3 output enable dif 3 hi ? z for nb3n1200k enabled rw 1 dif_3, dif_3# low/low for NB3W1200L 4 output enable dif 4 hi ? z for nb3n1200k enabled rw 1 dif_4, dif_4# low/low for NB3W1200L 5 output enable dif 5 hi ? z for nb3n1200k enabled rw 1 dif_5, dif_5# low/low for NB3W1200L 6 output enable dif 6 hi ? z for nb3n1200k enabled rw 1 dif_6, dif_6# low/low for NB3W1200L 7 output enable dif 7 hi ? z for nb3n1200k enabled rw 1 dif_7, dif_7# low/low for NB3W1200L t able 22. byte 2: output enable control register bit description if bit = 0 if bit = 1 type default output(s) affected 0 output enable dif 8 hi ? z for nb3n1200k enabled rw 1 dif_8, dif_8# low/low for NB3W1200L 1 output enable dif 9 hi ? z for nb3n1200k enabled rw 1 dif_9, dif_9# low/low for NB3W1200L 2 output enable dif 1 0 hi ? z for nb3n1200k enabled rw 1 dif_10, dif_10# low/low for NB3W1200L 3 output enable dif 11 hi ? z for nb3n1200k enabled rw 1 dif_11, dif_11# low/low for NB3W1200L 4 reserved 5 reserved 6 reserved 7 reserved
nb3n1200k, NB3W1200L http://onsemi.com 21 t able 23. byte 3: oe_[7:0]# pins real time readback control register bit description if bit = 0 if bit = 1 type default output(s) affected 0 reserved 0 1 reserved 0 2 reserved 0 3 reserved 0 4 reserved 0 5 reserved 0 6 reserved 0 7 reserved 0 t able 24. byte 4: oe_[1 1:8]# pins real time readback control register bit description if bit = 0 if bit = 1 type default output(s) affected 0 reserved 0 1 reserved 0 2 reserved 0 3 reserved 0 4 reserved 0 5 reserved 0 6 reserved 0 7 reserved 0 t able 25. byte 5: vendor/revision identifica tion control register bit description if bit = 0 if bit = 1 type default 0 vendor id bit 0 1111 = on semiconductor r 1 vendor id 1 vendor id bit 1 r 1 2 vendor id bit 2 r 1 3 vendor id bit 3 r 1 4 revision code bit 0 0011 r x revision code 5 revision code bit 1 r x 6 revision code bit 2 r x 7 revision code bit 3 r x
nb3n1200k, NB3W1200L http://onsemi.com 22 t able 26. byte 6: device id control register bit description if bit = 0 if bit = 1 type 1200k 1200l 0 device id 0 1200k = 120d = 78hex 1200l = 130d = 82hex r 0 0 1 device id 1 r 0 1 2 device id 2 r 0 0 3 device id 3 r 1 0 4 device id 4 r 1 0 5 device id 5 r 1 0 6 device id 6 r 1 0 7 device id 7 (msb) r 0 1 t able 27. byte 7: byte count register bit description if bit = 0 if bit = 1 type default 0 bc0 ? w riting to this register configures how many bytes will be read back rw 0 1 bc1 ? w riting to this register configures how many bytes will be read back rw 0 2 bc2 ? w riting to this register configures how many bytes will be read back rw 0 3 bc3 ? w riting to this register configures how many bytes will be read back rw 1 4 bc4 ? w riting to this register configures how many bytes will be read back rw 0 5 reserved 0 6 reserved 0 7 reserved 0 t able 28. byte 8 and beyond: vendor specific bit description if bit = 0 if bit = 1 type default 0 reserved 0 1 reserved 0 2 reserved 0 3 reserved 0 4 reserved 0 5 reserved 0 6 reserved 0 7 reserved 0
nb3n1200k, NB3W1200L http://onsemi.com 23 buffer power ? up state machine t able 29. buffer power ? up st a te machine state description 0 3 . 3 v buffer power off 1 after 3.3 v supply is detected to rise above 1.8 v?2.0 v, the buffer enters state 1 and initiates a 0.1 ms?0.3 ms delay. 2 buffer waits for a valid clock on the clk input and pwrdn# de ? assertion 3 once the pll is locked to the clk_in input clock, the buffer enters state 3 and enables outputs for normal operation. (notes 47, 48) 4 7 . t h e total power up latency from power on to all outputs active must be less than 1.8 ms (assuming a valid clock is present o n clk_in input). 4 8 . if power is valid and powerdown is de ? asserted but no input clocks are present on the clk_in input, dif clocks must remain disabled. only after valid input clocks are detected, valid power , pwrdn# de ? asserted with the pll locked/stable and the dif outputs enabled. figure 15. buffer power ? up state diagram state 0 state 3 power off normal operation state 1 delay 0.1 ms ? 0.3 ms state 2 powerdown asserted wait for input clock and powerdown de ? assertion no input clock
nb3n1200k, NB3W1200L http://onsemi.com 24 t able 30. dif clock output current board t arget t race/t erm z reference r, i ref = v dd /(3*r r ) output current v oh @ z 100 r ref = 475 1%, i ref = 2 . 32 ma i oh = 6*i ref 0.7 v @ 50 85 r ref = 412 , 1%, i ref = 2 . 67 ma i oh = 6*i ref 0.7 v @ 43.2 nmos push ? pull buffer specifications for NB3W1200L low power nmos push ? pull differential buffer the NB3W1200L utilizes the low ? power output buf fer for all dif ferential clocks. this buf fer uses ef ficient nmos push ? pull drivers powered of f a low voltage rail, of fering a reduction in power consumption, improved edge rate performance, and cross point voltage control. figure 16. nmos push ? pull buffer diagram clock rs rs source terminated 2 pf 2 pf receiver 3.3 v core 3.3 v 0.8 v nominal zo = 20 ohms clock# t ? line 10 typical t ? line 10 typical power filtering example ferrite bead power filtering recommended ferrite bead filtering equivalent to the following: 600 impedance at 100 mhz, 0.1 dcr max., 400 ma current rating. figure 17. schematic example of the nb3n1200k / NB3W1200L power filtering place at pin ferrite fb1 v3p3 c1 10 f c10 1 f c9 1 f 2.2 r1 vdda vddr 2.2 r2 c7 0.1 f c8 0.1 f vdd_diff vdd_diff c2 0.1 f c4 0.1 f c3 0.1 f c5 0.1 f c5 0.1 f c5 0.1 f c5 0.1 f vdd for pll vdd for input receiver
nb3n1200k, NB3W1200L http://onsemi.com 25 t ermination of differential outputs t able 31. nb3n1200k resistive lumped test loads for differential clocks clock board trace impedance r s r p ri ref units diff clocks ? 50 configuration 100 33 5% 49 . 9 1% 475 1% diff clocks ? 43 configuration 85 27 5% 42 . 2 1% 412 1% t able 32. NB3W1200L resistive lumped test loads for differential clocks clock board trace impedance r s r p ri ref units diff clocks ? 50 configuration 100 33 5% n/a n/a diff clocks ? 43 configuration 85 27 5% n/a n/a termination of differential hcsl type outputs (nb3n1200k) figure 18. 0.7 v configuration test load board termination for hcsl nb3n1200k nb3n1200k clock 1% 2 pf 5% 2 pf 5% rp rp rs rs tla = 10 in. tla = 10 in. clock# 475 t ermination of differential nmos push ? pull t ype outputs (NB3W1200L) figure 19. 0.7 v configuration t est load board t ermination for nmos push ? pull NB3W1200L NB3W1200L clock rs rs source t erminated 2 pf 2 pf receiver clock# t ? line 10 typical t ? line 10 typical
nb3n1200k, NB3W1200L http://onsemi.com 26 p ackage dimensions qfn64 9x9, 0.5p (punch & sa wn) case 485dh issue o soldering footprint dimensions: millimeters 9.30 6.40 6.40 0.50 0.62 0.32 64x 64x pitch 9.30 package outline recommended notes: 1. dimensioning and t olerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies t o pla ted terminal and is measured between 0.15 and 0.25mm from the terminal tip 4. coplanarity applies t o the exposed p ad as well as the terminals. 5. all dimensions appl y t o both the sa wn and punch p ackages. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 9.00 bsc d2 5.90 6.25 e 9.00 bsc 6.25 e2 5.90 e 0.50 bsc l 0.30 0.50 l1 0.00 0.15 l1 det ail a l alternate constructions l ??? ??? det ail b mold cmpd exposed cu al terna te construction top view a b pin one indica t or al terna te construction 0.15 c top view d a b e 0.15 c pin one indicator 2x 2x sea ting a3 a a1 side view 0.10 c 0.08 c c plane note 4 a3 side view det ail b al terna te construction alternate construction 1 64 bott om view 17 33 49 1 64 bott om view 17 33 49 d2 a m 0.10 b c l 64x e2 a m 0.10 b c b 64x e e/2 note 3 a m 0.10 b c m 0.05 c det ail a detail c det ail c al terna te construction l o n semi conduct o r and are regist ered trademarks of semiconduct o r co mponent s indust r ies, llc (sci llc). sci llc owns the right s to a numb er of pat ent s, trademarks, copyright s, trade secret s, and ot her int e llect ual propert y . a list ing of sci llc? s product / pat ent coverage may be accessed at ww w . onsemi. com/ sit e/ pdf / p at ent ? marking. pdf . sci llc reserves t h e r i ght t o m a ke c hanges w i t hout f u rt her n o t i ce t o a n y p r oduct s h e rein. s c i llc m a kes n o w a rrant y , r epresent at ion o r g uarant ee r egarding t h e s u it abilit y o f i t s p r oduct s f o r a n y par t i cular pur pose, nor does sci llc assume any liabilit y ar ising out of the applicat ion or use of any pr oduct or cir c uit , and s pecif ically disclaims any and all liabilit y , including wit hout limit at ion s pecial, c onsequent ial o r i n cident al d a mages. ? t ypical? p a ramet e rs w h ich m a y b e p r ovided i n s c i llc d a t a s heet s a nd/ or s pecif icat ions c a n a n d d o v a ry i n d i f f erent a pplicat ions and act ual perf ormance may vary over time. all operat ing parame ters, including ?t ypicals? must be validat ed for each cust omer applicat ion by cust omer ? s technical expert s . sci llc does n o t c onvey a n y l i cense under i t s p a t ent r i ght s n o r t h e r i ght s o f o t hers. s c i llc p r oduct s a r e n o t d e signed, i n t ended, o r a ut horized f o r u s e as c o mponent s in s yst ems int ended f o r surgical i m plant i n t o t h e b ody , o r o t her a pplicat ions i n t ended t o s upport o r s u st ain l i f e , o r f o r a n y o t her a pplicat ion i n w h ic h t h e f a ilure o f t h e s c i llc p r oduct c ould c r eat e a s i t uat ion w here personal i n jury o r d eat h m a y o ccur . s hould b u yer p u rchase o r u s e s c i llc p r oduct s f o r a n y s u ch u n int ended o r u naut horized appli cat i on, b u yer s hall i ndemnif y a n d h o ld sci llc a n d it s o f f i cer s , e m ployees, s ubsidiar i es, a f f iliat e s, a n d d i st r i but or s h a r m less a gainst a l l c l aims, c o st s, d a mages, a n d e x penses, a n d r easonable a t t o rney f ees a r ising o u t o f , d i rect ly o r i ndirect ly , any c l aim o f p e rsonal injury o r d eat h associat ed wit h s u ch unin t ended or u naut horized use, e v en if s u ch c l aim a lleges t hat s c i l lc was negligent r egarding the design or m anuf act u re of t h e part . sci llc is an equal opport unit y / a f f irmat i ve act i on employer . this lit e rat u re is subject t o all applicable copyrig ht laws and is not f o r resale in any manner . publica tion ordering informa tion n. american t echnical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa t echnical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nb3n1200k/d intel is a registered trademark of intel corporation. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver , colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 t oll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 t oll free usa/canada email : orderlit@onsemi.com on semiconductor w ebsite : www .onsemi.com order literature : http://www .onsemi.com/orderlit for additional information, please contact your local sales representative

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